1. Field of the Invention
Generally, the present disclosure relates to the fabrication of highly sophisticated integrated circuits requiring the deposition of silicon oxide materials with superior across-substrate uniformity, and particularly relates to semiconductor devices including transistor elements that comprise a high-k metal gate electrode structure in combination with an embedded strain-inducing semiconductor alloy.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the deposition and patterning of dielectric, semiconductive and conductive materials in order to form circuit elements on a given chip area according to a specified circuit layout. In many complex semiconductor devices, in addition to the many complex processes, frequently silicon dioxide, which is a well-established dielectric material in semiconductor devices, has to be deposited with very uniform characteristics across the semiconductor die and also across the entire substrate in order to ensure uniform performance of individual circuit elements, such as field effect transistors, which represent one important type of circuit element in complex integrated circuits. In recent developments of advanced MOS technologies, which is one of the most promising approaches for forming highly complex circuits due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency, performance of field effect transistors is improved by applying highly complex mechanisms, which may require very uniform oxide layers. For example, during the fabrication of complex integrated circuits using MOS technology, millions of transistors, e.g., N-channel transistors and/or P-channel transistors are formed on the substrate that includes a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions, i.e., an interface formed by highly doped regions, referred to as drain and source regions, with an inversely doped region, such as a channel region, disposed adjacent to the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the dopant concentration, the mobility of the charge carriers and, for a planar transistor architecture, the distance between the source and drain regions, which is also referred to as channel length.
Presently, the greater part of integrated circuits are formed on the basis of silicon due to its substantially unlimited availability, the well-understood characteristics of silicon and related materials and processes and the experience gathered during the past 50 years. Therefore, silicon will likely remain the material of choice for future circuit generations designed for mass products. One reason for the importance of silicon in fabricating semiconductor devices has been the superior characteristics of a silicon/silicon dioxide interface that allows reliable electrical insulation of different silicon regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and, thus, allows performing subsequent high temperature processes, as are required, for example, for anneal cycles to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface.
For the reasons pointed out above, in field effect transistors, silicon dioxide has been preferably used as a base material for gate insulation layers that separate the gate electrode, frequently comprised of polysilicon, from the silicon channel region. In steadily improving device performance of field effect transistors, the length of the channel region has been continuously decreased to improve switching speed and drive current capability. Since the transistor performance is controlled by, among other things, the voltage supplied to the gate electrode to invert the surface of the channel region to a sufficiently high charge density for providing the desired drive current for a given supply voltage, a certain degree of capacitive coupling, provided by the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween, has to be maintained. It turns out that decreasing the channel length for a planar transistor configuration requires an increased capacitive coupling, in combination with sophisticated lateral and vertical dopant profiles in the drain and source regions to avoid the so-called short channel behavior during transistor operation. The short channel behavior may lead to an increased leakage current and to a pronounced dependence of the threshold voltage on the channel length. Aggressively scaled planar transistor devices with a relatively low supply voltage and thus reduced threshold voltage may suffer from an exponential increase of the leakage current due to the required enhanced capacitive coupling of the gate electrode to the channel region. That is, conventionally, the thickness of the silicon dioxide layer has been correspondingly reduced to provide the required capacitance between the gate and the channel region. For example, a channel length of approximately 0.08 μm may require a gate dielectric made of silicon dioxide as thin as approximately 1.2 nm. Therefore, the relatively high leakage current caused by the direct tunneling of charge carriers through an ultra-thin silicon dioxide gate insulation layer may reach values for an oxide thickness in the range of 1-2 nm that may no longer be compatible with requirements for many types of circuits.
For this reason, new strategies have been developed in overcoming the limitations imposed by high leakage currents of extremely thin silicon oxide-based gate insulation layers. One very promising approach is the replacement of the conventional dielectric materials, at least partially, by dielectric materials having a dielectric constant that is significantly greater than the dielectric constant of silicon dioxide-based materials. For example, dielectric materials, also referred to as high-k dielectric materials, with a dielectric constant of 10.0 and significantly higher, may be used, for instance in the form of hafnium oxide, zirconium oxide and the like. In addition to providing a high-k dielectric material in the gate insulation layers, appropriate metal-containing materials may also have to be incorporated since the required work function values for P-channel transistors and N-channel transistors may not be obtained on the basis of standard polysilicon gate materials in combination with the high-k dielectric material. To this end, appropriate metal-containing materials may be provided so as to cover the sensitive high-k dielectric materials and act as a source for incorporating an appropriate metal species, such as lanthanum, aluminum and the like, in order to appropriately adjust the work function for N-channel transistors and P-channel transistors, respectively. Furthermore, due to the presence of a metal-containing conductive material, the generation of a depletion zone, as may typically occur in polysilicon-based electrode materials, may be substantially avoided.
The process of fabricating a sophisticated gate electrode structure on the basis of a high-k dielectric material may require a moderately complex process sequence in order to adjust an appropriate work function for the transistors of different conductivity type and due to the fact that high-k dielectric materials may typically be very sensitive when exposed to certain process conditions, such as high temperatures in the presence of oxygen and the like. Therefore, different approaches have been developed, such as providing the high-k dielectric material at an early manufacturing stage and processing the semiconductor devices with a high degree of compatibility with standard process techniques, wherein the typical electrode material polysilicon may be replaced in a very advanced manufacturing stage with appropriate metals for adjusting the work function of the different transistors and for providing a highly conductive electrode metal.
In other approaches the sophisticated gate electrode structures may be formed in an early manufacturing stage, while the further processing is based on many well-established process strategies. In this case, the high-k dielectric material and any metal species for adjusting the work function may be provided prior to or upon patterning the gate electrode stack, which comprises well-established materials, such as silicon and silicon/germanium.
In addition to providing sophisticated gate electrode structures, transistor performance may also be significantly enhanced by using a strain component in the channel region of at least one type of transistor, such as in P-channel transistors. It is well known that providing a compressive strain component along the current flow direction in a silicon channel region having a standard crystalline configuration may result in superior mobility of holes in the channel region, thereby also improving the drive current capability of the P-channel transistor. For this reason, a plurality of strain-inducing mechanisms have been developed, wherein one promising approach may be based on a strain-inducing semiconductor alloy, which is embedded into the active region of P-channel transistors after patterning the gate electrode structure. To this end, cavities may be formed in the active region laterally adjacent to the gate electrode structure and the cavities are subsequently refilled with a strain-inducing semiconductor alloy, such as a silicon/germanium material, which is grown in a strained state that in turn induces a desired compressive strain component in the channel region. The strain-inducing silicon/germanium material may be deposited on the basis of selective epitaxial growth techniques, in which process parameters are adjusted such that significant material deposition is restricted to crystalline silicon areas, while any material deposition on dielectric surface areas is suppressed. In order to avoid undue material growth on the gate electrode structures, the polysilicon material has to be reliably confined at least during the selective epitaxial growth process. For this purpose, the gate electrode structures are typically provided with a dielectric cap material, such as a silicon nitride material, and a silicon nitride spacer layer is typically provided so as to cover the N-channel transistors, while the silicon nitride spacer layer is patterned into sidewall spacer elements at the gate electrode structure of the P-channel transistor, wherein, in the same etch sequence, the corresponding cavities are also formed in the active region of the P-channel transistor.
Since the dielectric cap material has to be removed in a later manufacturing stage, it turns out that the incorporation of the strain-inducing semiconductor alloy in the P-channel transistor may significantly affect production yield in manufacturing strategies in which sophisticated high-k metal gate electrode structures are to be provided, as will be explained in more detail for a replacement gate approach with reference to FIGS. 1a-1b. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 comprising a substrate 101, above which is formed a silicon-based semiconductor layer 102. The substrate 101 and the semiconductor layer 102 may represent a silicon-on-insulator (SOI) configuration, when a buried insulating material (not shown) is positioned between the substrate 101 and the semiconductor layer 102. In other cases, a “bulk” configuration is provided, when the semiconductor layer 102 represents a portion of a crystalline material of the substrate 101. The semiconductor layer 102 comprises a plurality of “active regions,” such as semiconductor regions 102A, 102B, which are to be understood as semiconductor regions, in which appropriate dopant profiles are to be established so as to form PN junctions of one or more transistor elements. For example, the active region 102A represents a semiconductor region having an appropriate basic doping so as to correspond to an N-channel transistor 150A, while the semiconductor region 102B may represent a P-channel transistor 150B. The semiconductor regions 102A, 102B are laterally delineated in the semiconductor layer 102 by an isolation structure 102C, for instance a shallow trench isolation.
Moreover, in the manufacturing stage shown, a first gate electrode structure 160A is formed on the active region 102A and comprises a gate insulation layer 161, for instance in the form of a silicon dioxide-based material, possibly in combination with a high-k dielectric material, such as hafnium oxide and the like, while, in other approaches, the high-k dielectric material may be provided in a later manufacturing stage. Moreover, the gate electrode structure 160A comprises a silicon material 162 and a dielectric cap layer 163A, such as a silicon nitride material. Furthermore, a sidewall spacer structure 164 in the form of a silicon nitride material is provided in the gate electrode structure 160A. Similarly, a gate electrode structure 160B is formed on the active region 102B and comprises the components 161, 162, and 164. Furthermore, a dielectric cap layer 163B in the form of a silicon nitride material is provided, wherein typically the dielectric cap layer 163B may have a reduced thickness compared to the dielectric cap layer 163A, which may result in significant yield loss during the further processing of the device 100. Furthermore, a “gate electrode structure” 160C is provided so as to extend above the active region 102B and the isolation structure 102C and above the active region 102A. The electrode structure 160C may represent any appropriate polysilicon line for connecting the active regions 102A, 102B or the structure 160C may represent actual gate electrode structures of transistors formed in the active regions 102A, 102B, respectively. The electrode structure 160C also comprises a gate insulation layer 161, at least above the active regions 102A, 102B, and the silicon material 162. Moreover, a dielectric cap layer 163C is formed on the silicon material 162 and may have a different thickness caused by the preceding processing of the device 100. In some cases, even a substantially non-covered surface area 162C may have been produced during the preceding manufacturing processes, which may also negatively affect the further processing of the device 100. Moreover, in the manufacturing stage shown, a strain-inducing semiconductor alloy 151, such as a silicon/germanium alloy is formed in cavities 103, which are provided in the active region 102B laterally adjacent to the gate electrode structure 160B.
The semiconductor device 100 as illustrated in FIG. 1a may be formed on the basis of the following processes. First, the active regions 102A, 102B are geometrically defined in view of their lateral position, size and shape by forming the isolation structure 102C, which is accomplished by forming trenches in the semiconductor layer 102 using appropriate lithography techniques and subsequently refilling the trenches with an appropriate insulating material, such as silicon dioxide, silicon nitride and the like. Next, the basic doping, i.e., the well doping, is established in the active regions 102A, 102B in accordance with the required characteristics of the transistors 150A, 150B, which may be accomplished by using well-established masking regimes in combination with implantation processes. Next, the gate dielectric material 161 is formed, for instance by oxidation and/or deposition, depending on the process strategy. For instance, if a high-k dielectric material is to be provided in this manufacturing stage, any appropriate deposition techniques are used for forming the high-k dielectric material on a corresponding thin layer of a conventional dielectric material, such as silicon dioxide, silicon oxynitride and the like. If required, an appropriate cap material, such as a conductive cap material (not shown), may be provided so as to confine the high-k dielectric material. Thereafter, the silicon material 162 is deposited, for instance by well-established low pressure chemical vapor deposition (CVD) techniques, followed by the deposition of the silicon nitride material of the cap layers 163A, 163B, and 163C. Furthermore, any further materials, such as hard mask materials, for instance in the form of amorphous carbon and the like, are deposited and are subsequently patterned on the basis of sophisticated lithography and etch techniques, thereby finally forming the gate electrode structures 160A, 160B, 160C, having the required critical dimensions, which may correspond to a gate length, i.e., in FIG. 1a, the horizontal extension of the electrode material 162, of 40 nm and less.
After the corresponding gate patterning process, the gate electrode structures 160A, 160B, 160C comprise the dielectric cap materials 163A, 163B, 163C with substantially the same thickness, which may be approximately 40 nm. Thereafter, a spacer layer comprised of silicon nitride material is deposited by any appropriate process technique, such as multilayer deposition, low pressure CVD and the like, in order to obtain the desired material characteristics for the sidewall spacers 164. Subsequently, a resist mask is provided so as to cover the active region 102A and the corresponding part of the isolation structure 102C, while the active region 102B and the adjacent portion of the isolation structure 102C are exposed. On the basis of the corresponding resist mask, an anisotropic etch process is performed so as to first etch through the silicon nitride material of the spacer layer, thereby forming the sidewall spacers 164 on the gate electrode structure 160B and at the right hand side of the gate electrode structure 160C. Upon further continuing the etch process, based on an appropriate etch chemistry, the cavities 103 may be formed in the active region 102B, wherein a lateral offset from the electrode material 162 of the gate electrode structures 160B, 160C is determined by the width of the previously produced spacer elements 164. When forming the cavities 103, however, also the cap layer 163B and the exposed portion of the cap layer 163C are exposed to the reactive etch ambient, thereby increasingly removing material from these layers, which may finally result in the reduced thickness, as is shown in FIG. 1a. After the etch process, the resist mask is removed and any required cleaning processes are performed so as to prepare the device 100 for a subsequent selective epitaxial growth process for refilling the cavities 103 with the silicon/germanium material 151.
As previously explained, during the selective epitaxial growth process, a significant deposition of material 151 on dielectric surface areas is suppressed so that the spacer layer still formed above the semiconductor region 102A, the gate electrode structure 160A and the electrode structure 160C may suppress, in combination with the spacer structures 164, a material deposition. On the other hand, the material 151 may be efficiently deposited in the cavities 103, while the cap layer 163B in combination with the sidewall spacer structure 164 may confine the electrode material 162. Next, the spacer layer formed above the active region 102A and a portion of the isolation structure 102C is patterned so as to form the sidewall spacer elements 164 of the gate electrode structure 160A and the corresponding portion of the electrode structure 160C, which may be accomplished by forming a resist mask above the active region 102B and the corresponding portion of the electrode structure 160C. It should be appreciated that a certain degree of material erosion may also occur in the cap layer 163A upon patterning the spacer layer, however, at a significantly lesser extent compared to the material loss in the cap layer 163B, which has also experienced the cavity etch process. Furthermore, depending on the alignment accuracy for forming the corresponding resist masks, one of which protects the semiconductor region 102A when etching the cavities 103, and another one of which covers the semiconductor region 102B when patterning the spacer layer so as to form the spacer structure 164 of the gate electrode structure 160A, a significant loss of material may be observed in the spacer layer 163C, when a corresponding portion may be exposed twice to a reactive etch ambient. Consequently, a moderately high probability may exist for producing the substantially exposed surface portion 162C in the transition area of the shared electrode structure 160C. Consequently, the further processing is continued on the basis of a significant difference in layer thickness of the dielectric cap layers 163A, 163B, while also a significant difference in thickness may exist within the cap layer 163C, which may even include the substantially exposed surface portion 162C.
FIG. 1b schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage. As illustrated, the device 100 comprises drain and source regions 152 in the active regions 102A, 102B, in combination with metal silicide regions 154. Furthermore, a spacer structure 155 is formed on the sidewalls of the gate electrode structures 160A, 160B and 160C. Additionally, an interlayer dielectric material 120 or at least a portion thereof is formed so as to enclose the gate electrode structures 160A, 160B, 160C, and comprises, for instance, a silicon nitride layer 121 in combination with a silicon dioxide material 122.
The device 100 as illustrated in FIG. 1b may be formed on the basis of any appropriate process strategy. For example, after patterning the gate electrode structures 160A, 160B, 160C, the drain and source regions 152 in combination with the spacer structure 155 may be formed, for instance, by applying an appropriate masking regime for covering the active region 102B and a corresponding part of the isolation structure 102C in order to introduce appropriate dopant species into the active region 102A, thereby forming a first portion of the drain and source regions 152, such as an extension region. Upon masking the active region 102A and the associated part of the isolation structure 102C, the corresponding dopant species may be incorporated into the active region 102B. The implantation sequence may be performed on the basis of a dedicated offset spacer structure (not shown) which may be used to appropriately adjust the lateral offset of the dopant species for the extension regions and for any other dopant species, such as halo dopant species and the like. Thereafter, the spacer structure 155 may be formed by using deposition and etch techniques, followed by a further implantation sequence for completing the drain and source regions 152. Thereafter, anneal processes are performed in order to adjust the final dopant profile. In some cases, a metal silicide 154, as indicated in FIG. 1b, may be formed by providing an appropriate refractory metal, such as nickel and the like, and initiating a chemical reaction by performing a heat treatment. During the silicidation process, however, also metal silicide may form in any exposed surface portion, such as the portion 162C, thereby generating a metal silicide 154C. Similarly, the reduced thickness of the cap layer 163B may result in an increased probability of creating metal silicide residues within the semiconductor material 162.
It should be appreciated that the above-described complex process sequence may require a plurality of deposition processes and etch processes, many of which may exhibit a significant dependency on pattern density. That is, the deposition rate and/or the etch rate of any such complex processes may depend on the density of device features, such as gate electrode structures, that are provided per unit area. For example, in device areas in which the number of gate electrode structures per unit area is moderately high, the resulting deposition rate and etch rate may differ from device areas in which a lower number of gate electrode structures per unit area is provided. For example, densely packed device areas, such as static RAM areas, are considered as device areas having a high pattern density, since a plurality of closely spaced gate electrode structures and thus transistors are typically provided in these device regions. Consequently, any irregularities, as discussed above, for instance with the difference in thickness of the cap layers 163A, 163B, the width of any spacer structures and the like, may also significantly depend on the local pattern density, which may thus contribute to a pronounced variation of transistor characteristics, such as threshold voltage, current drive capability and the like.
During the further processing of the semiconductor device 100, the interlayer dielectric material 120, for instance comprising the layers 121 and 122, may be formed on the basis of well-established plasma enhanced CVD techniques and the like, followed by a planarization process. Furthermore, during a further process, the materials 162 of the gate electrode structures 160A, 160B, 160C has to be exposed in order to be replaced with any appropriate electrode materials, work function adjusting species, high-k dielectric materials and the like. To this end, the process 104 may typically comprise a chemical mechanical planarization (CMP), process wherein, however, the difference in thickness of the cap materials 163A, 163B (FIG. 1a) may result in extremely complex process conditions, in particular if a significant variation across the entire die and substrate is taken into consideration, as discussed above. Consequently, a reliable exposure is difficult to achieve during the process 104 and may thus require pronounced over-polish time, thereby even further contributing to a pronounced non-uniformity of the resulting device configuration. Moreover, in the case that metal silicide regions have been formed, any unwanted metal silicide residues may negatively affect the subsequent selective etch processes for removing the polysilicon material 162. For example, well-established etch chemistries, such as TMAH (tetra methyl ammonium hydroxide) may be used, which may, however, not efficiently remove, for instance, metal silicide or any other material residues, such as silicon dioxide, silicon nitride and the like.
Consequently, upon forming complex high-k metal gate electrode structures in accordance with a replacement gate approach, significant yield loss, or at least pronounced variations of device characteristics, may be caused during the above-described process sequence. The incorporation of a strain-inducing semiconductor material into the drain and source areas of P-channel transistors is an extremely efficient performance enhancing mechanism which, however, may also be the reason for pronounced transistor variations, in particular upon further scaling the overall transistor dimensions. In view of this situation, it has been proposed to at least reduce the dependency on pattern density and in particular the difference in thickness of the dielectric cap layers 163A, 163B and 163C upon forming an embedded strain-inducing semiconductor material. To this end, a further hard mask material may be used, for instance in the form of a silicon dioxide layer, which may be provided prior to forming the cavities 103 of FIG. 1a. In this case, the spacer structure 164 may be formed on the basis of a silicon nitride material that may be patterned commonly for P-channel transistors and N-channel transistors, thereby also exposing the cap layers 163A, 163B to substantially the same process conditions, which may thus result in a substantially identical thickness of these cap materials. Thereafter, the silicon dioxide layer may be provided and patterned in order to expose the P-channel transistor and thereafter corresponding etch processes may be applied, which may be more selective with respect to silicon nitride compared to the conventional process regime, as described above. In this case, the silicon nitride consumption upon forming the cavities 103 may be reduced, wherein, however, it has been observed that nevertheless a pronounced difference in thickness may occur. Furthermore, providing the additional hard mask material in the form of a silicon dioxide material, such as an undoped silicon dioxide material, may not efficiently address the problem of increased dependency on pattern density, thereby still resulting in pronounced variations across the die and also across entire substrates. Consequently, although theoretically providing a thin silicon dioxide hard mask material may provide less critical process conditions, it nevertheless turns out that, upon further device scaling, significant device variations may be observed.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.